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About This Manual
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Organization
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1    OEM Platform Requirements and Restrictions
1.1    PCI/ISA Modular Single-Board Computers (SMARTengine/Alpha and EBMnn)
1.1.1    Verifying CPU Version
1.1.2    Firmware Requirements
1.1.3    Installing Tru64 UNIX
1.1.4    Restrictions and Known Problems
1.1.4.1    Option Card Restrictions
1.1.4.2    PBXGB-AA (TGA2 PowerStorm 3D30) Video Card Restrictions
1.1.4.2.1    EV5 Alias Jumper Setting (SMARTengine/Alpha 21264 and EBM2n Only)
1.1.4.2.2    VGAEN Jumper Settings
1.1.4.2.3    X Server DMA Writes Must Be Disabled for Some Configurations
1.1.4.3    Operator Control Panel and Watchdog Timer Supported Only in Hardware and Firmware
1.1.4.4    IDE Device Mapping Potentially Impacts 21264 SBC Upgrades
1.1.5    Configuring PCI/ISA Modular 8-Headed Graphics Systems
1.1.5.1    Hardware and Software Requirements
1.1.5.2    Hardware Setup
1.1.5.3    Software Setup
1.1.6    Writing PCI Bus Device Drivers
1.2    Alpha VME 4/nnn and 5/nnn Single-Board Computers (EBVnn)
1.2.1    Verifying CPU Version
1.2.2    Firmware Requirements
1.2.3    Installing Tru64 UNIX
1.2.4    Configuring the VMEbus
1.2.5    Restrictions and Known Problems
1.2.5.1    VMEbus Autovectors Not Supported
1.2.5.2    Network Port Termination Required
1.2.5.3    Some TGA Video Card Configurations Require Disabling X Server DMA Writes
1.2.5.4    Master Block Transfer Restrictions
1.2.6    Writing VMEbus Device Drivers
1.3    AXPvme Single-Board Computers
1.3.1    Firmware Upgrade Required
1.3.2    Master Block Transfer Restrictions
 
2    Configuring the VMEbus for Alpha VME Systems
2.1    VMEbus Support Overview
2.2    Configuring VIP/VIC-Based Alpha VME SBCs
2.2.1    Configuring the vba_vipvic Subsystem
2.2.1.1    Specifying the VMEbus Request Level
2.2.1.2    Specifying the VIC Arbitration Mode
2.2.1.3    Specifying the VMEbus Fairness Timer Value
2.2.1.4    Specifying Bus Timeout Periods
2.2.1.5    Specifying the VMEbus Release Mode
2.2.1.6    Specifying System Controller VMEbus Resets
2.2.1.7    Special Considerations for VMEbus Resets
2.2.1.8    Specifying VMEbus Master Write Posting
2.2.1.9    Specifying the VMEbus DMA Interleave Gap
2.2.1.10    Specifying Limits on VMEbus DMA Reads
2.2.1.11    Specifying Limits on VMEbus DMA Writes
2.2.1.12    Specifying the DMA Method for SMP
2.2.2    Configuring VMEbus A32 and A24 Address Spaces
2.2.2.1    Specifying A32 and A24 Address Space Overlapping
2.2.2.2    Configuring A32 and A24 Window Sizes
2.2.2.3    Specifying the A32 Base Address
2.2.2.4    Specifying the A24 Base Address
2.2.3    Configuring the VMEbus A16 Address Space
2.2.4    Configuring VMEbus Interrupts
2.2.4.1    VMEbus Interrupt Request Levels
2.2.4.2    Setting VMEbus Interrupt Vector Parameters
2.2.4.3    Specifying Autovector Interrupt Vectors
2.2.4.4    Specifying Module Switch Interrupt Vectors
2.2.4.5    Specifying Global Switch Interrupt Vectors
2.2.5    Using VMEbus Hardware Byte-Swapping Modes
2.2.6    Sharing Memory Between Big Endian and Little Endian Processors
2.2.7    Performing VMEbus Slave Block Transfers
2.2.8    Performing VMEbus Master Block Transfers with Local DMA
2.2.8.1    Routines for Master Block-Mode Transfers
2.2.8.2    Restrictions on VMEbus Master Block Transfers
2.2.9    Using the Realtime Interrupt-Handling Routine rt_post_callout
2.3    Configuring UNIVERSE II-Based Alpha VME SBCs
2.3.1    Configuring the vba_univ Subsystem
2.3.1.1    Specifying the Adapter Interrupt Dispatch Policy
2.3.1.2    Specifying the Adapter PCI Scatter/Gather Maximum Size
2.3.1.3    Specifying the Adapter DMA Window Maximum Size
2.3.1.4    Specifying the PCI Coupled Window Timer Value
2.3.1.5    Specifying the PCI Maximum Retries
2.3.1.6    Specifying the PCI Posted Write Transfer Count
2.3.1.7    Specifying the PCI Aligned Burst Size
2.3.1.8    Specifying the VMEbus Request Level
2.3.1.9    Specifying the VMEbus Request Mode
2.3.1.10    Specifying the VMEbus Release Mode
2.3.1.11    Specifying the VMEbus Timeout Period
2.3.1.12    Specifying the VMEbus Arbitration Mode
2.3.1.13    Specifying the VMEbus Arbitration Timeout Period
2.3.1.14    Specifying System Controller VMEbus Resets
2.3.1.15    Special Considerations for VMEbus Resets
2.3.1.16    Specifying the VMEbus On and Off Counters for MBLTs
2.3.2    Configuring PCI-to-VME Address Spaces
2.3.2.1    Enabling or Disabling a PCI-to-VME Window
2.3.2.2    Specifying a PCI-to-VME Window VMEbus Base Address
2.3.2.3    Specifying a PCI-to-VME Window Size
2.3.2.4    Specifying PCI-to-VME Window VMEbus Address Modifiers
2.3.2.5    Specifying a PCI-to-VME Window VMEbus Maximum Data Width
2.3.2.6    Specifying PCI-to-VME Window Write Posting
2.3.2.7    Specifying a PCI-to-VME Window VMEbus Cycle Type
2.3.3    Configuring a Special A24/A16 PCI-to-VME Window
2.3.3.1    Enabling or Disabling the A24/A16 Window
2.3.3.2    Specifying A24/A16 Window Write Posting
2.3.3.3    Specifying the A24/A16 Window VMEbus Maximum Data Width
2.3.4    Configuring VME-to-PCI Address Spaces
2.3.4.1    Enabling or Disabling a VME-to-PCI Window
2.3.4.2    Specifying a VME-to-PCI Window VMEbus Base Address
2.3.4.3    Specifying a VME-to-PCI Window Size
2.3.4.4    Specifying VME-to-PCI Window VMEbus Address Modifiers
2.3.4.5    Specifying VME-to-PCI Window Write Posting
2.3.4.6    Specifying VME-to-PCI Window Prefetch Reads
2.3.4.7    Specifying VME-to-PCI Window 64-Bit PCI Bus Transactions
2.3.5    Mapping UNIVERSE II CSRs to the VMEbus
2.3.5.1    Enabling or Disabling the CSR Window
2.3.5.2    Specifying a CSR Window VMEbus Base Address
2.3.5.3    Specifying CSR Window VMEbus Address Modifiers
2.3.6    Mapping a Location Monitor Window to the VMEbus
2.3.6.1    Enabling or Disabling the Location Monitor Window
2.3.6.2    Specifying a Location Monitor Window VMEbus Base Address
2.3.6.3    Specifying Location Monitor Window VMEbus Address Modifiers
2.3.7    Configuring VMEbus Interrupts
2.3.7.1    VMEbus Interrupt Request Levels
2.3.7.2    Setting VMEbus Interrupt Vector Parameters
2.3.7.3    Specifying Module Switch Interrupt Vectors
2.3.7.4    Specifying Location Monitor Interrupt Vectors
2.3.8    Using VMEbus Software Byte Swapping
2.3.9    Sharing Memory Between Big Endian and Little Endian Processors
2.3.10    Performing VMEbus Slave Block Transfers
2.3.11    Performing VMEbus Master Block Transfers with Local DMA
2.3.11.1    Routines for Master Block-Mode Transfers
2.3.11.2    Restriction on VMEbus Master Block Transfers
2.3.12    Using the Realtime Interrupt-Handling Routine rt_post_callout
 
3    Configuring a VMEbus Backplane (vb) Network
3.1    VMEbus Backplane (vb) Network Overview
3.1.1    VMEbus Addresses Used for Client Communication
3.1.2    VMEbus Addresses Used for Interrupting
3.1.3    Box Manager Node
3.1.4    Network Participation
3.2    Configuring vb Network Nodes
3.3    Modifying vb Driver Attributes
3.3.1    Modifying Per-Node vb Attributes
3.3.2    Modifying Per-Network vb Attributes
3.4    Modifying vba_vipvic Adapter Attributes
3.5    Modifying vba_univ Adapter Attributes
3.6    VIP/VIC Two-Node Network Example
3.7    UNIVERSE II Two-Node Network Example
3.8    Related ioctl Commands
3.9    Diagnostic Messages
3.10    Errors
3.10.1    System Startup Error Messages
3.10.2    Post-Startup Error Messages
 
Tables
1-1    Supported PCI/ISA Backplanes and Kernels
1-2    PCI/ISA Options Supported Behind the Bridge
2-1    VIP/VIC VMEbus Adapter Defaults
2-2    VIP/VIC VMEbus Interrupt Initial Defaults
2-3    VIP/VIC VMEbus Interrupt Request Levels
2-4    UNIVERSE II VMEbus Adapter Defaults
2-5    UNIVERSE II VMEbus Interrupt Initial Defaults
2-6    UNIVERSE II VMEbus Interrupt Request Levels
3-1    VMEbus Backplane (vb) Network Driver Defaults
3-2    VIP/VIC VMEbus Address Space Defaults
 
Index